The present disclosure relates generally to integrated circuit devices that employ a power distribution network. More particularly, the present disclosure relates to reset sequencing of certain circuitry components that share the power distribution network to reduce power distribution noise.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Numerous electronic devices—including computers, tablets, calculators, televisions, gaming devices, and mobile phones, to name just a few—operate using integrated circuit devices. Integrated circuit devices are made of many different circuitry components that may draw power from a shared power distribution network. For example, integrated circuit devices such as application-specific integrated circuits (ASICs) or programmable logic device (PLDs) may include, transceivers, digital signal processing (DSP) circuitry components, phase-locked loops (PLLs), and/or dynamic random access memory (DRAM) memory circuitry components, among others. During normal operation, the circuitry components of the integrated circuit device may operate dynamically, drawing variable amounts of power from a shared power distribution network at various times. These dynamic events may produce voltage transients in the power distribution network. The dynamic events may include dynamic reset, dynamic circuit reconfiguration, external clock changes, and the like. Simultaneous dynamic events on multiple circuitry components may result in cumulative voltage transients large enough to cause circuit errors or failures in the circuitry components that share the power distribution network.
As an example, modern programmable logic devices, such as field programmable gate array (FPGA) or application specific integrated circuits (ASIC) devices, may contain many transceiver channels. In many device designs, it is not uncommon for these transceiver channels to be used orthogonally to each other. That is, several channels may be grouped together to form a peripheral circuitry component interconnect express (PCIe) interface while other channels may be used to support an Ethernet interface, and still other channels may be used to support Interlaken interfaces. Resetting or dynamically reconfiguring multiple channels in these interfaces may create enough of a power distribution network disturbance to create bit errors on the unrelated PCIe or Ethernet interfaces.